ROCKCHIP MIPI DPHY WITH INNO IP BLOCK

Required properties:
 - compatible : must be one of:
	"rockchip,rk1808-mipi-dphy";
	"rockchip,rv1126-mipi-dphy";
 - reg : the address offset of register for mipi-dphy configuration.
 - #phy-cells : must be 0. See ./phy-bindings.txt for details.
 - clocks and clock-names:
	- the "pclk" clock is required by the phy module, used to register
	  configuration
	- the "ref" clock is used to get the rate of the reference clock
	  provided to the PHY module
 - clock-output-names: from common clock binding.
	See ../clocks/clock-bindings.txt for details.
 - #clock-cells : from common clock binding; shall be set to 0.
 - resets : phandle to the reset of MIPI DSI PHY APB clock.
 - reset-names : should be "apb".

Example:
	mipi_dphy: mipi-dphy@ff370000 {
		compatible = "rockchip,rk1808-mipi-dphy";
		reg = <0x0 0xff370000 0x0 0x500>;
		clocks = <&cru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
		clock-names = "ref", "pclk";
		clock-output-names = "mipi_dphy_pll";
		#clock-cells = <0>;
		resets = <&cru SRST_MIPIDSIPHY_P>;
		reset-names = "apb";
		#phy-cells = <0>;
		rockchip,grf = <&grf>;
		status = "disabled";
	};