<html><head><meta name="color-scheme" content="light dark"></head><body><pre style="word-wrap: break-word; white-space: pre-wrap;">From a20c4e8738a00087aa5d53fe5148ed484e23d229 Mon Sep 17 00:00:00 2001
From: Robert Marko &lt;robimarko@gmail.com&gt;
Date: Sat, 31 Dec 2022 13:56:26 +0100
Subject: [PATCH] arm64: dts: qcom: ipq8074: add CPU OPP table

Now that there is NVMEM CPUFreq support for IPQ8074, we can add the OPP
table for SoC.

Signed-off-by: Robert Marko &lt;robimarko@gmail.com&gt;
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 52 +++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -42,6 +42,7 @@
 			clocks = &lt;&amp;apcs_glb APCS_ALIAS0_CORE_CLK&gt;;
 			clock-names = "cpu";
 			#cooling-cells = &lt;2&gt;;
+			operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;
 		};
 
 		CPU1: cpu@1 {
@@ -53,6 +54,7 @@
 			clocks = &lt;&amp;apcs_glb APCS_ALIAS0_CORE_CLK&gt;;
 			clock-names = "cpu";
 			#cooling-cells = &lt;2&gt;;
+			operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;
 		};
 
 		CPU2: cpu@2 {
@@ -64,6 +66,7 @@
 			clocks = &lt;&amp;apcs_glb APCS_ALIAS0_CORE_CLK&gt;;
 			clock-names = "cpu";
 			#cooling-cells = &lt;2&gt;;
+			operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;
 		};
 
 		CPU3: cpu@3 {
@@ -75,6 +78,7 @@
 			clocks = &lt;&amp;apcs_glb APCS_ALIAS0_CORE_CLK&gt;;
 			clock-names = "cpu";
 			#cooling-cells = &lt;2&gt;;
+			operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;
 		};
 
 		L2_0: l2-cache {
@@ -84,6 +88,54 @@
 		};
 	};
 
+	cpu_opp_table: opp-table {
+		compatible = "operating-points-v2-kryo-cpu";
+		nvmem-cells = &lt;&amp;cpr_efuse_speedbin&gt;;
+		opp-shared;
+
+		opp-1017600000 {
+			opp-hz = /bits/ 64 &lt;1017600000&gt;;
+			opp-microvolt = &lt;1&gt;;
+			opp-supported-hw = &lt;0xf&gt;;
+			clock-latency-ns = &lt;200000&gt;;
+		};
+
+		opp-1382400000 {
+			opp-hz = /bits/ 64 &lt;1382400000&gt;;
+			opp-microvolt = &lt;2&gt;;
+			opp-supported-hw = &lt;0xf&gt;;
+			clock-latency-ns = &lt;200000&gt;;
+		};
+
+		opp-1651200000 {
+			opp-hz = /bits/ 64 &lt;1651200000&gt;;
+			opp-microvolt = &lt;3&gt;;
+			opp-supported-hw = &lt;0x1&gt;;
+			clock-latency-ns = &lt;200000&gt;;
+		};
+
+		opp-1843200000 {
+			opp-hz = /bits/ 64 &lt;1843200000&gt;;
+			opp-microvolt = &lt;4&gt;;
+			opp-supported-hw = &lt;0x1&gt;;
+			clock-latency-ns = &lt;200000&gt;;
+		};
+
+		opp-1920000000 {
+			opp-hz = /bits/ 64 &lt;1920000000&gt;;
+			opp-microvolt = &lt;5&gt;;
+			opp-supported-hw = &lt;0x1&gt;;
+			clock-latency-ns = &lt;200000&gt;;
+		};
+
+		opp-2208000000 {
+			opp-hz = /bits/ 64 &lt;2208000000&gt;;
+			opp-microvolt = &lt;6&gt;;
+			opp-supported-hw = &lt;0x1&gt;;
+			clock-latency-ns = &lt;200000&gt;;
+		};
+	};
+
 	pmu {
 		compatible = "arm,cortex-a53-pmu";
 		interrupts = &lt;GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)&gt;;
</pre></body></html>