<html><head><meta name="color-scheme" content="light dark"></head><body><pre style="word-wrap: break-word; white-space: pre-wrap;">From f7ab709727e845ffdfc428ec2f236d0c1997b153 Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing &lt;kernel@esmil.dk&gt;
Date: Sat, 20 Nov 2021 21:33:08 +0100
Subject: [PATCH 1023/1024] RISC-V: Add StarFive JH7100 audio reset node

Add device tree node for the audio resets on the StarFive JH7100 RISC-V
SoC.

Signed-off-by: Emil Renner Berthing &lt;kernel@esmil.dk&gt;
---
 arch/riscv/boot/dts/starfive/jh7100.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -144,6 +144,12 @@
 			#clock-cells = &lt;1&gt;;
 		};
 
+		audrst: reset-controller@10490000 {
+			compatible = "starfive,jh7100-audrst";
+			reg = &lt;0x0 0x10490000 0x0 0x10000&gt;;
+			#reset-cells = &lt;1&gt;;
+		};
+
 		clkgen: clock-controller@11800000 {
 			compatible = "starfive,jh7100-clkgen";
 			reg = &lt;0x0 0x11800000 0x0 0x10000&gt;;
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