--- a/arch/arm64/boot/dts/mediatek/mt7988.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988.dtsi
@@ -365,6 +365,61 @@
 
 	};
 
+	tops: tops@09100000 {
+		compatible = "mediatek,tops";
+		reg = <0 0x09100000 0 0x01000000>;
+		reg-names = "tops-base";
+		clocks = <&topckgen CK_TOP_BUS_TOPS_SEL>,
+			 <&topckgen CK_TOP_TOPS_P2_26M_SEL>,
+			 <&topckgen CK_TOP_NETSYS_TOPS_400M_SEL>,
+			 <&topckgen CK_TOP_NPU_TOPS_SEL>,
+			 <&topckgen CK_TOP_CK_NPU_SEL_CM_TOPS_SEL>;
+		clock-names = "bus", "sram", "xdma", "offload", "mgmt";
+		power-domains = <&topmisc MT7988_POWER_DOMAIN_TOPS0>,
+				<&topmisc MT7988_POWER_DOMAIN_TOPS1>;
+
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "tdma-tx-pause", "mbox", "wdt";
+
+		dmas = <&hpdma1 0>;
+		dma-names = "tnl-sync";
+
+		fe_mem = <&eth>;
+	};
+
+	tops-mbox {
+		compatible = "mediatek,tops-mbox";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "mbox";
+		tops = <&tops>;
+	};
+
+	hpdma1: hpdma@09106000 {
+		compatible = "mediatek,hpdma-top";
+		reg = <0 0x09106000 0 0x1000>;
+		reg-names = "base";
+		#dma-cells = <1>;
+	};
+
+	hpdma2: hpdma@09606000 {
+		compatible = "mediatek,hpdma-sub";
+		reg = <0 0x09606000 0 0x1000>;
+		reg-names = "base";
+		#dma-cells = <2>;
+	};
+
+	tops-ocd@0e500000 {
+		compatible = "mediatek,tops-ocd";
+		reg = <0 0x0e500000 0 0x15000>;
+		reg-names = "tops-ocd-base";
+		clocks = <&infracfg_ao CK_INFRA_AUD_L>;
+		clock-names = "debugsys";
+	};
+
 	watchdog: watchdog@1001c000 {
 		compatible = "mediatek,mt7622-wdt",
 			     "mediatek,mt6589-wdt",